ZF SiliconAuto I/O Interface Chip for Automotive High-Performance Computers

At Embedded World 2026, ZF and SiliconAuto introduced the ZF SiliconAuto I/O interface chip designed for automotive high-performance computers. The new architecture focuses on integrating multiple automotive sensor interfaces with advanced processing capabilities in a single modular solution. The chip design targets next-generation vehicle computing platforms by enabling efficient sensor handling, real-time processing, and scalable performance needed for modern advanced driver assistance systems and automated driving technologies.

Integrated Sensor Processing and Safety Architecture

The chip design incorporates SiliconAuto’s XMotiv M3 microcontroller functioning as a safety controller within the system architecture. It integrates automotive sensor interface intellectual property along with embedded pre-processing capabilities, including low-latency camera image signal processing and on-chip radar signal processing. By processing sensor data directly on the chip, the architecture reduces computational pressure on central processors while improving system responsiveness and enabling faster decision-making for advanced driver assistance and automated vehicle functions.

Modular Chiplet Design for Scalable HPC Platforms

The architecture is produced using a lower-cost semiconductor processing node and follows a modular chiplet-based design that allows manufacturers to upgrade individual components without redesigning the entire high-performance computing platform. Optimized DRAM and SRAM structures improve energy efficiency by minimizing data transfers to external DDR memory, reducing system power consumption. This scalable computing solution supports a wide performance range, from entry-level ADAS implementations to complex SAE Level 4 automated driving systems while offering OEMs a flexible alternative to existing HPC architectures.