Allegro DVT Supports Automotive Base Die Development for Chiplet-Based Automotive SoCs

On June 30, Allegro DVT announced its contribution to the European CHASSIS program through the implementation of the Automotive Base Die chiplet. The Allegro DVT Automotive Base Die serves as the primary communication and integration hub for automotive System-on-Chip (SoC) infrastructure, enabling seamless interoperability between third-party chiplets using the Universal Chiplet Interconnect Express (UCIe) standard. This architecture is intended to simplify integration while supporting scalable and efficient next-generation automotive semiconductor platforms.

The Automotive Base Die is funded under the CHASSIS project within the Chips JU program by leading organizations including BMW, imec, and Bosch. Allegro DVT has contributed its Encoding and Decoding Semiconductor Video IP portfolio to help create optimized, high-performance video pipelines for chiplet-based automotive architectures. These technologies are designed to strengthen video processing capabilities while supporting modular semiconductor development across advanced automotive computing platforms in Europe.

The supplied video IP supports multiple in-vehicle camera applications, including ADAS, surround view, and in-vehicle infotainment systems capable of handling several high-resolution video streams simultaneously. By utilizing Allegro DVT's expertise in video compression and real-time video processing, the implementation is engineered to satisfy demanding automotive requirements related to memory bandwidth optimization, low processing latency, and reduced power consumption, helping enable efficient performance for future vehicle electronic architectures.

Frequently Asked Questions

What is the Automotive Base Die in the European CHASSIS program?
The Automotive Base Die is a central communication and integration hub designed for automotive System-on-Chip infrastructure within the European CHASSIS program. It enables third-party chiplets to connect through the Universal Chiplet Interconnect Express (UCIe) standard while supporting scalable semiconductor architectures. With contributions from Allegro DVT and funding through the Chips JU CHASSIS project involving BMW, imec, and Bosch, the platform is intended to improve integration efficiency, advanced video processing, and overall automotive computing performance for future vehicles.