aiMotive aiWare5 Enables Flexible Automotive AI Workloads

aiMotive and Cadence Demonstrate Flexible AI Processing

On September 23, aiMotive and Cadence demonstrated how individual neural network layers can execute on either aiMotive’s aiWare5 automotive NPU IP or Cadence Tensilica NeuroEdge 130 AI Co-Processor. The demonstration used pre-silicon simulation to examine how AI workloads could be distributed between different processing engines. The test focused on giving automotive chip designers greater flexibility when deciding how neural network workloads should run across available AI hardware. By testing multiple workload configurations, the teams showed how different engines could participate in the execution of the same neural network while using their default configurations rather than specially tuned settings.

Workload Partitioning Across Two AI Engines

The demonstration showed how automotive chip designers can divide AI workloads between different AI engines and toolchains, potentially reducing the need for complex manual graph partitioning and scheduling. Each neural network layer was manually assigned to one of the two engines during the test, allowing the teams to compare different workload arrangements directly. This approach provided a practical way to examine how individual layers could move between processing resources rather than requiring an entire network to remain on a single engine. The resulting configurations offered a basis for evaluating flexible AI execution across different automotive processing architectures.

aiWare5 Provides Automotive NPU Flexibility

aiWare5 was also demonstrated as a flexible automotive NPU IP designed for integration into different automotive computing architectures. Developed as a safety element out of context, aiWare5 is ISO 26262 ASIL B-certified and can be integrated into automotive SoCs, AI accelerators, and chiplets. Its role in the demonstration highlighted how an automotive NPU can participate in a broader processing environment rather than operating as the only AI engine available to a system. The test therefore examined aiWare5 as one component within a heterogeneous AI processing architecture where neural network layers can be assigned across multiple engines.

NeuroEdge 130 Works Alongside Different NPUs

Cadence Tensilica NeuroEdge 130 AI Co-Processor is designed to operate alongside different NPUs, and the demonstration paired it with aiWare5 to examine flexible AI processing across multiple architectures. The test provided an opportunity to assign neural network layers to either engine and observe how the workload could be distributed. Rather than requiring one processing architecture to handle every layer, the setup allowed the teams to explore combinations involving both engines. This capability is relevant to automotive chip development because designers can evaluate different processing arrangements during pre-silicon development before hardware implementation.

ResNet50 and DETR Workloads Tested

The teams tested both ResNet50 and DETR networks while changing how individual layers were assigned between the two AI engines. The configurations ranged from running the complete network on one engine to switching between aiWare5 and NeuroEdge 130 layer by layer. Both engines operated using their default configurations instead of being specially tuned for the demonstration. ResNet50 maintained comparable accuracy across the tested configurations, providing a basis for comparing workload execution under different assignments. DETR used random weights, allowing the teams to verify execution of a modern transformer-based network without making accuracy comparisons the primary focus of that test.

Pre-Silicon Simulation Enables Architecture Evaluation

Using pre-silicon simulation allowed the teams to examine workload distribution before physical silicon was available. This approach made it possible to test multiple assignments of neural network layers between aiWare5 and NeuroEdge 130 and compare how the two engines could be used together. The demonstration focused on execution flexibility rather than a specially optimized configuration, with both engines retaining their default settings. By evaluating ResNet50 and DETR across different layer assignments, the test illustrated how simulation can support architectural exploration and help chip designers assess heterogeneous AI processing strategies during development.

Industry Impact & Outlook

The demonstration highlights a broader automotive AI design approach in which different processing engines can share neural network workloads according to architectural requirements. For automotive chip designers, the ability to evaluate layer-level assignments between an NPU and AI co-processor can provide another method for exploring heterogeneous computing architectures during development. The combination of aiWare5 and NeuroEdge 130 also shows how multiple AI processing resources can be evaluated without requiring every workload configuration to rely on a single engine. Further development could focus on how such flexible partitioning strategies translate from pre-silicon simulation into production automotive SoCs, accelerators, and chiplet-based designs.

Frequently Asked Questions

What did aiMotive and Cadence demonstrate?
The teams demonstrated how individual neural network layers can run across aiWare5 and Tensilica NeuroEdge 130 AI Co-Processor using pre-silicon simulation. The test examined different workload assignments between the two engines, including configurations where an entire network ran on one engine and configurations where execution switched between engines layer by layer. ResNet50 maintained comparable accuracy across the tested configurations, while DETR used random weights to verify execution of a modern transformer-based network. Both engines used their default configurations rather than being specially tuned for the demonstration.